1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to the design of masks or reticles for use in multiple patterning processes, such as double patterning processes, that are performed to form hole-type or trench-type features, and the use of such masks or reticles in various photolithography systems to manufacture integrated circuit products.
2. Description of the Related Art
Photolithography is one of the basic processes used in manufacturing integrated circuit products. At a very high level, photolithography involves (1) forming a layer of light or radiation-sensitive material, such as photoresist, above a layer of material or a substrate, (2) selectively exposing the radiation-sensitive material to a light generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (interchangeable terms as used herein) to the radiation-sensitive material, and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.
Of course, the ultimate goal in integrated circuit fabrication is to faithfully reproduce the original circuit design on the integrated circuit product. Historically, the feature sizes and pitches (spacing between features) employed in integrated circuit products were such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced to the point where existing photolithography tools, e.g., 193 nm wavelength photolithography tools, cannot form single patterned mask layers with all of the features of the overall target pattern. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as double patterning. In general, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. The simplified, less-dense patterns are then printed separately on a wafer utilizing two separate masks (where one of the masks is utilized to image one of the less-dense patterns, and the other mask is utilized to image the other less-dense pattern). Further, in some cases, the second pattern is printed in between the lines of the first pattern such that the imaged wafer has, for example, a feature pitch which is half that found on either of the two less-dense masks. This technique effectively lowers the complexity of the photolithography process, improving the achievable resolution and enabling the printing of far smaller features than would otherwise be possible using existing photolithography tools.
FIGS. 1A-1D depict one illustrative double patterning process. An initial overall target pattern 10 that is comprised of nine illustrative trench features 12 is depicted in FIG. 1A. The space (or pitch) between the features 12 in the initial overall target pattern 10 is such that the initial overall target pattern 10 cannot be printed using a single mask with available photolithography tools. Thus, in this illustrative example, the initial overall target pattern 10 is decomposed into a first sub-target pattern 10A (comprised of the feature number 5) and a second sub-target pattern 10B (comprised of the features 1-4 and 6-9). The sub-target patterns 10A, 10B are referred to as “sub-target patterns” because each of them contain less than all of the features in the initial overall target pattern 10. The features that are incorporated in the sub-target patterns 10A, 10B are selected and spaced such that the features may be readily formed using available photolithography tools. Ultimately, when the mask design process is completed, data corresponding to the sub-target patterns 10A, 10B (modified as necessary during the design process) will be provided to a mask manufacturer that will produce a tangible mask (not shown) to be used in a photolithographic tool to manufacture integrated circuit products.
FIG. 1B depicts an illustrative wafer or substrate 22 having a material layer 20 formed thereabove. A hard mask layer 16 is formed above the material layer 20. A first patterned photoresist mask layer 14A is formed above the hard mask layer 16. The first patterned photoresist mask layer 14A was exposed using a mask corresponding to the first sub-target pattern 10A. That is, the first patterned photoresist mask 14A has an opening 15 that corresponds to feature number 5 shown in the first sub-target pattern 10A. As depicted in FIG. 1B, an etching process is performed through the first patterned photoresist mask layer 14A to defined a trench 17 (that corresponds to the feature 5) in the hard mask 16.
In FIG. 1C, the first patterned photoresist mask layer 14A has been removed and a second patterned photoresist mask layer 14B has been formed above the hard mask 16A. The second patterned photoresist mask layer 14B was exposed using a mask corresponding to the second sub-target pattern 10B. That is, the second patterned photoresist mask layer 14B has a plurality of openings 19 that correspond to feature numbers 1-4 and 6-9 shown in the second sub-target pattern 10B. The second patterned photoresist mask layer 14B covers the opening 17 defined using the first patterned photoresist mask layer 14A as shown in FIG. 1B. As depicted in FIG. 1C, an etching process is performed through the second patterned photoresist mask layer 14B to define a plurality of trenches 21 (that correspond to the features 1-4 and 6-9) in the patterned hard mask 16A.
In FIG. 1D, the second patterned photoresist mask 14B has been removed and one or more etching processes have been performed through the patterned hard mask 16A to define a patterned layer of material 20A comprised of a plurality of trenches 23. The trenches 23 define a pattern that corresponds to the features (1-9) in the overall target pattern 10.
It is well known that, for a variety of reasons, photolithography systems do not print exactly what is depicted in a theoretical target pattern, e.g., the lengths of line-type features may be shorter than anticipated, corners may be rounded instead of square, etc. Proximity effects may also cause features that otherwise have the same physical dimensions to print differently during photolithography processing. For example, a so-called “isolated” feature (e.g., a feature where there is no adjacent structure of a given distance of, for example, about 300-500 nm) will print with different dimensions than a so-called “densely-packed” feature (e.g., a feature with adjacent or nearby features) even though both the isolated feature and the densely-packed feature have the same target dimensions. Such variations are often referred to as process variations.
There are several factors that cause such process variations, such as interference between light beams transmitted through adjacent patterns, resist processes, the reflection of light from adjacent or underlying materials or structures, unacceptable variations in topography, etc. Due to such process variations, efforts are made to define and increase an associated process window that will allow formation of functionally acceptable features while accounting for the process variations described above. That is, mask designers seek to identify which aspects of a particular circuit pattern, e.g., a line length, a line width, etc., may be modified such that, accounting for the known process variations, acceptable patterns may be reliably and repeatedly formed in an underlying layer of material or a substrate. For example, in a process that is sometimes referred to as “re-targeting,” a line length may be increased or decreased or a line width (critical dimension) may be increased, etc. However, in some applications, the packing density and design rules for a particular circuit are such that there is no room for re-targeting certain features. As a result, in those situations, isolated features may have a very inefficient process window and only SRAFs may be employed to improve the process window of such features. While such SRAFs do improve the process window, they may give rise to reduced depth-of-focus issues. Moreover, as compared to densely-packed features, isolated features tend to have a smaller process window as they tend to be more sensitive to process variations.
The design and manufacture of reticles used in such photolithography processes is a very complex and expensive undertaking as such masks must be very precise and must enable the repeated and accurate formation of a desired pattern in the underlying layer of material (for an etching process). Mask designers have developed several techniques to try to counteract such process variations and to otherwise increase process windows so as to increase the manufacturability of a given circuit pattern. One technique involves the use of so-called sub-resolution assist features (SRAFs). A SRAF is a feature that is formed on a mask, but the size of the SRAF is less than the resolution capability of the particular photo-lithography tool. Accordingly, while the SRAFs that are present on the mask have an impact on the exposure process, they will not be replicated or printed on the layer of photoresist that is exposed using the mask containing the SRAFs. Typically, a plurality of SRAFs are positioned on a mask adjacent to an isolated feature in an effort to get the isolated feature to print more like a densely-packed feature. Another technique sometimes employed to reduce process variations involves the use of so-called print assist features (PRAFs) on masks. In contrast to SRAFs, PRAFs are of a size such that they will print on the exposed layer of photoresist. Such PRAFs are also typically provided on a mask adjacent to an isolated feature in an effort to get the isolated feature to print more like a densely-packed feature. One example of the use of PRAFs involves the formation of a plurality of PRAFs that correspond to “dummy” gate electrode structures adjacent to an isolated gate electrode structure that is to be formed for an integrated circuit device. The dummy gate electrodes are never intended to function as gate electrodes, but they are actually printed in an effort to reduce or eliminate process variations during the formation of the desired, isolated gate electrode. In some cases, such PRAFs are subsequently removed.
The present disclosure is directed to the design of masks or reticles for use in multiple patterning processes, such as double patterning processes, that are performed to form hole-type or trench-type features, and the use of such masks or reticles in various photolithography systems to manufacture integrated circuit products.